Engineering

For junior/senior/graduate-level courses in Computer Organization in departments of Computer Science and Computer Engineering.

This text provides a clear, comprehensive presentation of the organization and architecture of modern-day computers, emphasizing both fundamental principles and the critical role of performance in driving computer design. The text conveys concepts through a wealth of concrete examples highlighting modern CISC and RISC systems.

• NEW - Expanded and current coverage of innovations and improvements in the field.

  • Keeps students up-to-date with the latest technology and captures the rapid pace of change that characterizes the industry.

• NEW - An entire chapter devoted to cache memory—(Ch. 4).

  • Explores a central element in the design of high-performance processors, as well as the complex and important topic of cache design.

• Added chapter on IA-64/Itanium architecture—Describes and analyzes the underlying principles of predicated execution and speculative loading.

  • Familiarizes students with recent concepts central to the design of the new architecture from Intel and Hewlett-Packard.

• NEW - Expanded and updated chapter on parallel organization—Covers SMPs, clusters, and NUMA systems descriptions.

  • Allows students to make detailed comparisons among symmetric multiprocessors (SMPs), clusters, and non-uniform memory access (NUMA) systems.

• NEW - Expanded optical memory coverage.

  • Gives students updated information on magneto-optical memory devices and more.

• NEW - Improved illustrations—Features figures and tables.

  • Clarifies content and concepts throughout the text.

• Unique Superscalar design chapter—(Ch. 14).

  • Introduces students to an approach that dominates the microprocessor design field, including the widely used Pentium.

• Unified, complete coverage of instruction set architecture—With rich set of examples (Chs. 10 & 11).

  • Explains why certain design features are chosen, and enables students to evaluate instruction set design issues.

• Detailed treatment of bus organization and specifications—Includes the important example of PCI.

  • Focuses students on the functioning of buses around which virtually all microprocessors are organized, and enables them to evaluate key design issues.

• Interaction of I/O modules with the outside world and the CPU—Includes important external interface examples of Infiniband and FireWire.

  • Demonstrates the function and structure of I/O so that students gain a complete understanding of the subject.

• Broad presentation of RISC technology.

  • Unifies important design features found in almost all contemporary machines, including Pentium II and III.

• Unified treatment of internal and external memory—Covers leading-edge areas such as magneto-optical; advanced DRAM; and RAID disk arrays.

  • Enhances students' understanding of hierarchy elements, from cache to optical memory.

• Numerous running examples—Especially Pentium 4 and PowerPC G4.

  • Illustrates systems that encompass many of the contemporary design initiatives.

• Full treatment of microprogrammed implementation—Not usually covered in other texts.

  • Gives students a firm grasp on this area so that they can truly understand processor organization.

• Approximately 200 homework problems—With a range of difficulty.

  • Provides students with the opportunity to test and expand their understanding of chapter material.

• Chapter-end review questions.

  • Ensures students have read and absorbed key content before moving on.

• Chapter-end recommended websites and reading lists.

  • Encourages students to obtain additional and advanced information on subjects discussed in the text.

• Up-to-date coverage of EPIC.

  • Familiarizes students with another modern architectural approach—this one seen in the IA-64 architecture of Intel's Itanium.

• Thorough coverage of computer arithmetic—(Ch. 9).

  • Teaches student twos complement and floating point representations and arithmetic, with detailed examination of IEEE 754.

• Expanded and current coverage of innovations and improvements in the field.

  • Keeps students up-to-date with the latest technology and captures the rapid pace of change that characterizes the industry.

• An entire chapter devoted to cache memory—(Ch. 4).

  • Explores a central element in the design of high-performance processors, as well as the complex and important topic of cache design.

• Expanded and updated chapter on parallel organization—Covers SMPs, clusters, and NUMA systems descriptions.

  • Allows students to make detailed comparisons among symmetric multiprocessors (SMPs), clusters, and non-uniform memory access (NUMA) systems.

• Expanded optical memory coverage.

  • Gives students updated information on magneto-optical memory devices and more.

• Improved illustrations—Features figures and tables.

  • Clarifies content and concepts throughout the text.

I. OVERVIEW.

II. THE COMPUTER SYSTEM.

III. THE CENTRAL PROCESSING UNIT.

IV. THE CONTROL UNIT.

V. PARALLEL ORGANIZATION.

Computer Architecture  [CORE TEXTS]   (Electrical and Computing Engineering)
Computer Organization and Architecture  (Computer Science)

• 
  Computer Organization and Architecture: Designing for Performance, 8/E
  Stallings
  ©2010 | Prentice Hall | Cloth; 792 pp | Instock
  ISBN-10: 0136073735 | ISBN-13: 9780136073734
  URL:  prenhall.com/stallings
  Brief Description | Buy from myPearsonStore

  

  For undergraduates and professionals in computer science, computer engineering, and electrical engineering courses.

   

  Learn the fundamentals of processor and computer design from the newest edition of this award winning text.

   

  Four-time winner of the best Computer Science and Engineering textbook of the year award from the Textbook and Academic Authors Association, Computer Organization and Architecture: Designing for Performance provides a thorough discussion of the fundamentals of computer organization and architecture, covering not just processor design, but memory, I/O, and parallel systems.Coverage is supported by a wealth of concrete examples emphasizing modern RISC, CISC, and superscalar systems.

   

  The eighth revision has been updated to reflect major advances in computer technology, including multicore processors and embedded processors. Interactive simulations have been expanded and keyed into relevant sections of text.

WILLIAM STALLINGS has made a unique contribution to understanding the broad sweep of technical developments in computer networking and computer architecture. He has authored 17 titles, and counting revised editions, a total of 35 books on various aspects of these subjects. Far five years in a row, he has been the recipient of the award for the best Computer Science and Engineering textbook of the year from the Textbook and Academic Authors Association.

In over 25 years in the field, Dr. Stallings has been a technical contributor, technical manager and an executive with several high-technology firms. He is an independent consultant whose clients have included computer and networking manufacturers and customers, software development firms and leading-edge government research institutions. He created and maintains the Computer Science Student Resource Site at:

WilliamStallings.com/StudentSupport.html

Dr. Stallings holds a Ph.D. from MIT in computer science and a B.S. from Notre Dame in electrical engineering.

William Stallings' book provides comprehensive and completely up-to-date coverage of computer organization and architecture including memory, I/O, and parallel systems. The text covers leading-edge areas, including superscalar design, IA-64 design features, and parallel processor organization trends. It meets students' needs by addressing both the fundamental principles as well as the critical role of performance in driving computer design. Providing an unparalleled degree of instructor and student support, including supplements and online resources through the book's website, the sixth edition is in the forefront in its field.

• IA-64/Itanium architecture: chapter-length description and analysis that includes predicated execution and speculative loading.
• Cache memory: Cache memory is a central element in the design of high-performance processors. An entire chapter is devoted to this issue in the new edition.
• Optical memory: expanded and updated.
• Advanced DRAM architecture: more material has been added to cover this topic, including an updated discussion of SDRAM and RDRAM.
• SMP's, clusters, and NUMA systems: the chapter on parallel organization has been expanded and updated.
• Expanded instructor support: the book now provides extensive support for projects with its new website.
• Pedagogy: each chapter now includes a list of review questions (as well as homework problems) and a list of key words.

• Running examples: numerous concrete examples, especially Pentium 4 and Power PC G4.
• Bus organization: detailed treatment and evaluation of key design issues.
• RISC: broad, unified presentation.
• Microprogrammed implementation: full treatment for a firm grasp.
• I/O functions and structures: provides full understanding and shows interaction of I/O modules with the outside world and the CPU.
• Unified instructional approach: enables student to evaluate instruction set design issues.
• Instructors Resource CD-ROM: includes solutions to homework problems, list of research projects, list of simulation projects plus student manual for both SimpleScalar and SMPCache, and a list of suggested reading assignments.

WilliamStallings.com provides support for students, instructors and professionals:

Interwrite Personal Response System
EduCue, Addison-Wesley & Benjamin Cummings
©2004 | Prentice Hall | Electronic Supplement | Instock
ISBN-10: 0321267354 | ISBN-13: 9780321267351

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