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Fully updated for the latest versions of Verilog HDL, this complete reference progresses logically from the most fundamental Verilog concepts to today's most advanced digital design techniques. Written for both experienced students and newcomers, it offers broad coverage of Verilog HDL from a practical design perspective. One step at a time, Samir Palnitkar introduces students to gate, dataflow (RTL), behavioral, and switch level modeling; presents the Programming Language Interface (PLI); describes leading logic synthesis methodologies; explains timing and delay simulation; and introduces many other essential techniques for creating tomorrows complex digital designs. Palnitkar offers a wealth of proven Verilog HDL modeling tips, and more than 300 fully-updated illustrations, examples, and exercises. Each chapter contains detailed learning objectives and convenient summaries.

• NEW - Fully updated for the latest versions of Verilog HDL.

  • Helps students gain mastery over Verilog HDL's most important new features and capabilities.

• Broad coverage, from the fundamentals to the state-of-the-art—Logically progresses from basic techniques for building and simulating small Verilog models to advanced techniques for constructing tomorrow's most sophisticated digital designs.

  • Gives students a single source for all they need to know about Verilog HDL, from introductory-level techniques to the leading edge.

• Extensive examples, illustrations, and exercises—Illuminates every aspect of Verilog HDL design with practical examples and hands-on exercises.

  • Gives students maximum visual support and hands-on practice for mastering Verilog HDL rapidly, and retaining what they've learned.

• Learning objectives and summaries in every chapter—Includes many features designed to promote easier learning and deeper mastery.

  • Helps students prepare to learn new concepts, and then review what they have learned.

• CD-ROM—SILOS III simulation environment by Simucad, Inc.

  • Verilog simulator with a graphic users interface and the source code for examples in the book.

• Fully updated for the latest versions of Verilog HDL.

  • Helps students gain mastery over Verilog HDL's most important new features and capabilities.

(NOTE: Each chapter concludes with a Summary and Exercises.)

About the Author.


Foreword.


Preface.


Acknowledgments.

I. BASIC VERILOG TOPICS.

II. ADVANCED VERILOG TOPICS.

III. APPENDICES.

Advanced Digital Design/Logic  [PTG: PRENTICE HALL PROFESSIONAL]   (Electrical & Computing Engineering)

About the Author

Samir Palnitkar is a recognized authority on Verilog HDL, modeling, verification, logic synthesis, and EDA-based methodologies in digital design. He has worked extensively with design and verification on various successful microprocessor, ASIC, and system projects. He was the lead developer of the Verilog framework for the shared memory, cache coherent, multiprocessor architecture, popularly known as the UltraSPARCTM Port Architecture, defined for Sun's next generation UltraSPARC-based desktop systems. Besides the UltraSPARC CPU, he has worked on a number of diverse design and verification projects at leading companies including Cisco, Philips, Mitsubishi, Motorola, National, Advanced Micro Devices, and Standard Microsystems.

VERILOG HDL, Second Editionby Samir PalnitkarWith a Foreword by Prabhu Goel

Written forboth experienced and new users, this book gives you broad coverage of VerilogHDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.

Among its many features, this edition—

• Describes state-of-the-art verification methodologies

• Provides full coverage of gate, dataflow (RTL), behavioral and switch modeling

• Introduces you to the Programming Language Interface (PLI)

• Describes logic synthesis methodologies

• Explains timing and delay simulation

• Discusses user-defined primitives

• Offers many practical modeling tips

Includes over 300 illustrations, examples, and exercises, and a Verilog resource list.Learning objectives and summaries are provided for each chapter.

The CD-ROM contains a Verilog simulator with agraphical user interface and the source code for the examples in the book.

Whatpeople are saying about Verilog HDL—

“Mr.Palnitkar illustrates how and why Verilog HDL is used to develop today’smost complex digital designs. This book is valuable to both the novice and theexperienced Verilog user. I highly recommend it to anyone exploring Verilogbased design."

—RajeevMadhavan, Chairman and CEO, Magma Design Automation

“Thisbook is unique in its breadth of information on Verilog and Verilog-relatedtopics. It is fully compliant with the IEEE 1364-2001 standard, contains allthe information that you need on the basics, and devotes several chapters toadvanced topics such as verification, PLI, synthesis and modelingtechniques.”

—MichaelMcNamara, Chair, IEEE 1364-2001 Verilog Standards Organization

Thishas been my favorite Verilog book since I picked it up in college. It is theonly book that covers practical Verilog. A must have for beginners andexperts.”

—BerendOzceri, Design Engineer, Cisco Systems, Inc.

“Simple,logical and well-organized material with plenty of illustrations, makes this anideal textbook.”

—Arun K. Somani, Jerry R. Junkins Chair Professor,Department of Electrical and Computer Engineering, Iowa State University, Ames

PRENTICE HALL

Professional Technical Reference

Upper Saddle River, NJ 07458

www.phptr.com

ISBN: 0-13-044911-3

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