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Advanced Digital Design with the Verilog HDL
Michael D. Ciletti

ISBN-10: 0130891614
ISBN-13: 9780130891617

Publisher: Prentice Hall
Copyright: 2003
Format: Cloth; 982 pp
Published: 08/13/2002
Status: Instock

Suggested retail price: $159.00
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For an advanced course in digital design for seniors and first-year graduate students in electrical engineering, computer engineering, and computer science.

This book builds on the student's background from a first course in logic design and focuses on developing, verifying, and synthesizing designs of digital circuits. The Verilog language is introduced in an integrated, but selective manner, only as needed to support design examples (includes appendices for additional language details). It addresses the design of several important circuits used in computer systems, digital signal processing, image processing, and other applications.

Brief review of basic principles in combinational and sequential logic.
- Prepares students to address advanced design using an HDL.

Focus on modern digital design methodology enabled by an HDL.
- Prepares students to practice a design methodology widely used by the industry.

Over 150 fully-verified examples and problems with a wide range of difficulty after each chapter.
- Allows students to download source files and run basic and advanced examples and solutions to problems.

Companion Website—Includes source files of all models developed in the examples, source files of testbenches for simulating all of the examples, solutions to selected problems, answers to frequently asked questions, tutorials, ASIC standard cell library with synthesis and timing database, along with many other helpful features.
- Provides students and instructors with another medium to collect information.

In-depth treatment of algorithms and architectures for digital machines.
- Presents design alternatives and tradeoffs, and shows how algorithms can be implemented in silicon.

Packaged CD-ROM with Silos III Verilog design environment and simulator and XILINX ISE synthesis tools.
- Allows students to develop, verify, and synthesize complex designs using powerful industry-quality tools having user-friendly interfaces, producing results that are ready to download to prototype evaluation boards.

In-depth treatment of synthesis for cell-based ASICs and FPGAs.
- Engages students in design, verification, and synthesis of hardware-based circuits, and teaches them how to anticipate the results of synthesis.

A set of XILINX FPGA-based lab-ready exercises linked to the book.
- Puts theory into practice, and challenges students to develop a hardware-oriented background in synthesis.

A set of classroom-ready transparency masters—Bundled free with XILINX student edition 4.2.
- Reduces preparation time for instructors and enables efficient use of classroom contact.

1. Introduction to Digital Design Methodology.

Design Methodology - An Introduction. IC Technology Options. Overview.

2. Review of Combinational Logic Design.

Combinational Logic and Boolean Algebra. Theorems for Boolean Algebraic Minimization. Representation of Combinational Logic. Simplification of Boolean Expressions. Glitches and Hazards. Building Blocks for Logic Design.

3. Fundamentals of Sequential Logic Design.

Storage Elements. Flip-Flops. Busses and Three-State Devices. Design of Sequential Machines. State Transition Graphs. Design Example: BCD to Excess-3 Code Converter. Serial Line Code Converter for Data Transmission. State Reduction and Equivalent States.

4. Introduction to Logic Design with Verilog.

Structural Models of Combinational Logic. Logic Simulation, Design Verification, and Testbenches. Propagation Delay. Truth Table Models of Combinational and Sequential Logic with Verilog.

5. Logic Design with Behavioral Models of Combinational and Sequential Logic.

Behavioral Modeling. A Brief Look at Data Types for Behavioral Modeling. Boolean Equation-Based Behavioral Models of Combinational Logic. Propagation Delay and Continuous Assignments. Latches and Level-Sensitive Circuits in Verilog. Cyclic Behavioral Models of Flip-Flops and Latches. Cyclic Behavior and Edge Detection. A Comparison of Styles for Behavioral Modeling. Behavioral Models of Multiplexers, Encoders, and Decoders. Dataflow Models of a Linear Feedback Shift Register. Modeling Digital Machines with Repetitive Algorithms. Machines with Multi-Cycle Operations. Design Documentation with Functions and Tasks: Legacy or Lunacy? Algorithmic State Machine Charts for Behavioral Modeling. ASMD Charts. Behavioral Models of Counters, Shift Registers, and Register Files. Switch Debounce, Metastability, and Synchronizers for Asynchronous Signals. Design Example: Keypad Scanner and Encoder.

6. Synthesis of Combinational and Sequential Logic.

Introduction to Synthesis. Synthesis of Combinational Logic. Synthesis of Sequential Logic with Latches. Synthesis of Three-State Devices and Bus Interfaces. Synthesis of Sequential Logic with Flip-Flops. Synthesis of Explicit State Machines. Registered Logic. State Encoding. Synthesis of Implicit State Machines, Registers, and Counters. Resets. Synthesis of Gated Clocks and Clock Enables. Anticipating the Results of Synthesis. Synthesis of Loops. Design Traps to Avoid. Divide and Conquer: Partitioning a Design.

7. Design and Synthesis of Datapath Controllers.

Partitioned Sequential Machines. Design Example: Binary Counter. Design and Synthesis of a RISC Stored Program Machine. Design Example: UART.

8. Programmable Logic and Storage Devices.

Programmable Logic Devices. Storage Devices. Programmable Logic Array (PLA). Programmable Array Logic (PALTM). Programmability of PLDs. Complex PLDs (CPLDs). Altera MAX 7000 CPLD. XILINX XC9500 CPLDs. Field Programmable Gate Arrays. Altera Flex 8000 FPGAs. Altera Flex 10 FPGAs. Altera Apex FPGAs. Altera Chip Programmability. XILINX XC4000 Series FPGA. XILINX Spartan XL FPGAs. XILINX Spartan II FPGAs. XILINX Virtex FPGAs. Embeddable and Programmable IP Cores for a System on a Chip (SOC). Verilog-Based Design Flows For FPGAs. Synthesis with FPGAs.

9. Architectures and Algorithms for Digital Processors.

Algorithms, Nested Loop Programs, and Data Flow Graphs. Design Example: Halftone Pixel Image Converter. Digital Filters and Signal Processors. Building Blocks for Signal Processors. Pipelined Architectures. Circular Buffers. Dual-Port Fifos and Synchronization Across Clock Domains.

10. Architectures for Arithmetic Processors.

Number Representation. Functional Units for Addition and Subtraction. Functional Units for Multiplication. Multiplication of Signed Binary Numbers. Multiplication of Fractions. Functional Units for Division.

11. Post-Synthesis Design Tasks.

Post-Synthesis Design Validation. Post-Synthesis Timing Verification. Elimination of ASIC Timing Violations. False Paths. Dynamically Sensitized Paths. System Tasks for Timing Verification. Fault Simulation and Testing. Fault Simulation. Fault Simulation with Verifault-XL. JTAG Ports and Design for Testability and BIST.

Appendices.

Verilog Primitives. Verilog Keywords. Verilog Nets. Verilog Data Types, Operators, and Precedence. Backus-Naur (BNF) Formal Syntax Notation. Verilog Language Formal Syntax. System Tasks and Functions. Compiler Directives. Rules for User Defined Primitives. Additional Features of Verilog. Verilog 2001. PLI. Websites. Web-based Tutorials.

Index.

Advanced Computer Architecture [CORE TEXTS] (Electrical and Computing Engineering)
Advanced Digital Design/Logic [CORE TEXTS] (Electrical and Computing Engineering)

Advanced Digital Design with the Verilog? HDL |
Backcover Copy

Behavioral modeling with a hardware description language (HDL) is the key to modern ASIC design. Readers preparing to contribute to a productive design team must know how to use a hardware description language at key stages of the design flow. This book is written for a course going beyond the basic principles and methods learned in a first course in digital design.

Our focus is on design methodology enabled by an HDL. Our goal is to build on a student's background from a first course in logic design by

reviewing basic principles of combinational and sequential logic,
introducing the use of HDLs in design,
emphasizing descriptive styles that will allow the reader to quickly design working circuits suitable for application-specific integrated circuit (ASIC) and/or field-programmable gate array (FPGA) implementation, and
providing in-depth design examples using modern design tools. Readers are encouraged to simplify, clarify, and verify their designs.

The Verilog hardware description language (IEEE Standard 1364) serves as a common framework supporting the design activities treated in this book, but our focus is on developing, verifying, and synthesizing designs of digital circuits, not on the Verilog language. Most students taking a second course in digital design will be familiar with at least one programming language and will be able to draw on that background in reading this text. We cover only the core and most widely used features of Verilog.

Chapter 1: Introduction to Digital Design Methodology
Chapter 2: Review of Combinational Logic Design
Chapter 3: Fundamentals of Sequential Logic Design
Chapter 4: Introduction to Logic Design with Verilog
Chapter 5: logic Design with Behavioral Models of Combinational and Sequential Logic
Chapter 6: Synthesis of Combinational and Sequential Logic
Chapter 7: Design and Synthesis of Datapath Controllers
Chapter 8: Programmable Logic and Storage Devices
Chapter 9: Algorithms and Architectures for Digital Processors
Chapter 10: Architectures for Arithmetic Processors
Chapter 11: Postsynthesis Design Tasks
Appendices

Companion Website - Ciletti
Ciletti
©2002 | Prentice Hall | On-line Supplement; 0 pp | Estimated Availability : 09/01/2002
ISBN-10: 0130938831 | ISBN-13: 9780130938831

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